Developing Fault Models for Nanowire Logic Circuits

It is widely acknowledged that nanoelectronic devices will suffer from more manufacturing and operational faults than classical CMOS devices in large-scale integrated circuits. The confident use of these emerging technologies relies on our capacity to better understand their fault mechanisms, and our ability to deduce related fault models. These challenging goals are addressed in this paper for nanowire logic circuits, which constitute one of the most promising technologies in the nanoelectronics realm. Fault models are proposed attending to how fault mechanisms manifest at device and logic abstraction levels. This research is framed within a more global investigation focused on the development of suitable dependability assessment methodologies and defect and fault tolerance strategies for systems built-up using nanodevices.